(1) Field of the Invention
The present invention relates to a method used to fabricate an insulator filled, shallow trench, isolation region for a semiconductor device.
(2) Description of Prior Art
Micro-miniaturization, or the use of sub-micron features, have allowed the semiconductor industry to increase the performance of semiconductor chips, while still reducing the processing cost of these same semiconductor chips. Micro-miniaturization has mainly been realized as a result of advances in semiconductor fabrication disciplines such as photolithography and dry etching. The use of more advanced exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron features to be routinely achieved in photoresist layers, while advances in dry etching tools and processes, have allowed the sub-micron features in overlying photoresist layers to be easily transferred to the underlying materials used for semiconductor chip fabrication. Semiconductor chips, with sub-micron features, result in reductions in performance degrading capacitances and resistances, thus improving device performance. In addition the use of sub-micron features allow smaller semiconductor chips to be created, however still exhibiting the same device densities achieved with larger chips, however reducing processing costs as a result of attaining more chips for a specific size substrate.
In addition to performance and cost objectives being realized via the use of sub-micron features, specific elements of semiconductor devices, have been modified to achieve additional performance and cost benefits. For example isolation regions, formed in non-device regions of the semiconductor chip, via LOCal Oxidation of Silicon, (LOCOS), can consume valuable area, via an unwanted "birds beak" phenomena. "Birds beak", or an encroachment of the isolation oxide region, under an insulator mask used to protect active device regions from the LOCOS process, results in unwanted consumption of a silicon region, that had allotted for the active device region. Therefore active device regions have to designed with larger areas, to accommodate for the encroachment effect, therefore resulting in larger semiconductor chips. The use of shallow trench isolation, (STI), in which a shallow trench is etched in a semiconductor substrate, followed by the filling of the trench with an insulator layer, allows the designed dimension of the isolation region to be achieved, without the encroachment phenomena experienced via the LOCOS isolation technology.
The formation of STI regions can however present unwanted device phenomena, such as a "kink effect", resulting from a recessing of insulator fill layer, at the edge of the shallow trench, during removal of a pad oxide layer, where the pad oxide layer is used a component of a composite insulator mask, used for STI definition. The recessing of the insulator layer, in the shallow trench, is predominately at the edges of the shallow trench, resulting in a thinner gate insulator layer, grown at the edge of the shallow trench, thus allowing premature turn on thresholds to occur. The "kink effect" refers to a "kink", or a break, in the curve relating drain--source current, (Ids), as a function of gate voltage, (Vg). This invention will describe a process for eliminating the thinning of the insulator layer, at the edges of the shallow trench, thus avoiding the unwanted "kink effect". This is accomplished by initially creating a "T" shaped insulator, in a shallow trench opening, featuring a top portion of the insulator shape, overlying the insulator layer in shallow trench, with the top portion of the "T" shaped insulator, wider than the shallow trench, thus located overlying a portion of the pad oxide layer, thus protecting the insulator fill, at the edge of the shallow trench, during the pad oxide removal procedure. Prior art, such as Yu, in U.S. Pat. No. 5,728,622, describes a LOCOS isolation region, with a "T" shape. However that prior art does not describe the "T" shape, STI region, and the process used for the STI region, described in this present invention.